The field of the present invention pertains to the deposition of gap fill materials over interconnect structures to fill in discontinuous or nonconforming topologies, methods of forming and depositing gap fill layers, and gap fill layers and semiconductor devices resulting therefrom.
As integrated circuits (IC""s) become more compact, dense and powerful, this necessarily also has decreased and continues to decrease the distances between adjacent components and interconnects. Due to this increasing density and the need for faster speeds, copper and copper alloys are again receiving attention as materials of choice for interconnects. Copper offers advantages over aluminum in that it has a lower resistivity than aluminum and exhibits superior electromigration properties.
Whether using copper or aluminum, the topography of stacks is becoming more dense and intricate. For example, a typical capacitor stack configuration has tended toward larger and larger aspect ratios to achieve greater surface area of the capacitor plates, thereby increasing the overall capacitance of the stack. These high aspect ratio formations are but one example of the increasing need for the ability to deposit a layer over steep, multi step formations, while achieving a smooth, flat and thickness consistent layer.
Many gap fill layers lack an adequate ability to flow so as to consistently cover high aspect ratio gaps and other step formations, resulting in unacceptable coverage, e.g., smaller gaps may still remain between the gap fill layer and the structure intended to be covered. For example, FIG. 2 shows a prior art layer 90 lacking adequate flow characteristics to completely conform to the topography of the stepped stack that it is applied over. The lack of flowability translates to a lack of conformability, with a greater buildup of the layer on the tops of the interconnects 92 forming areas of increased thickness 100. Also, the areas overlying the gaps are depressed so that the resulting topography of the layer 90 is not flat on top or conforming to the underlying topography. As for the gaps, the lack of flowability of the layer 90 causes it to leave gaps 98, which, although smaller than the gaps prior to adding the filling layer 90, are detrimental to the functioning and/or performance of the finished semiconductor product. Although FIG. 2 shows an example of a conventional stack in which aluminum interconnects 92 are deposited on a dielectric layer 94 overlying a substrate 96, it is noted that the same type of filling problems arise in stacks produced according to damascene and dual damascene techniques using copper, i.e., uneven filling layer thicknesses, lack of flatness of the filling layer, voids in the trenches and/or vias.
Additionally, when aspect ratios (i.e., height to width ratio of a gap) of the gaps are greater than those shown in FIG. 2, e.g., greater than about 2:1 and currently up to about 10:1, voids 102 can be left in the gaps as a result of the inability of the layer 90 to even reach the bottom of the gaps, as shown in FIG. 4. Again, this problem occurs with both conventional techniques as well as with damascene and dual damascene techniques employed with copper.
Attempts have been made to improve the flowability of fill layers by the formation of a dielectric layer produced by providing an organic silane layer, e.g., TEOS, in gas form and converting it to an oxide film by various CVD processes. In one example, a plasma enhanced CVD process uses an organic silane as a starting gas, and water is added to it to increase the surface wettability of the interface between the layer formed and the substrate on which the layer is formed. Thus, the dielectric layer formed is more likely to flow and result in a flatter surface of the finished layer, while also flowing together to prevent leaving voids. Although this method has low dependence on the shape of the substrate as to its flowability, the concentration of hydroxyl groups in the resulting layer is relatively high, and this causes a lower film quality.
A method of forming a dielectric fill layer has also been proposed in which the layer is produced by feeding an organic silane such as TEOS, and H2O2 into a CVD processing chamber, which react to form the oxide layer, see F. Gallard et al., xe2x80x9cHydrogen Peroxide and Silane CVD Process for Pre Metal Device Applicationsxe2x80x9d 1996 Proceedings Dielectrics for VLSI/ULSI Multilevel Interconnection Conference, February 20-21, Santa Clara, Va. The surface to which the dielectric layer is applied is wetted due to the water that is produced as a reaction product of the H2O2 reacting with the organic silane Also, the highest concentration of H2O2 that is commercially available is 60%, with the remainder being water. Thus, water is also taken up into the film causing the film quality to degrade. Also, since H2O2 is highly reactive, it is difficult to control its reactivity and it may prematurely react, at least in part, with the silane above the actual location in which the film is desired to be produced.
Another method of forming a dielectric layer is disclosed in U.S. Pat. No. 5,763,018, in which a plasma enhanced CVD process is used to deposit water molecules and plasma-dissociated products of water molecules on a substrate where a dielectric layer is intended to be formed. The dielectric layer is then formed by injecting a silicon containing gas, e.g., TEOS, and an oxidant, e.g., ozone, which react to form an oxide layer on the substrate. This process also runs the risk of prematurely reacting at least some of the TEOS with the oxidant and water vapor, either above the substrate surface or even in the feed pipe, since TEOS oxidant and water vapor are fed into the chamber together through a single input.
Thus, there remains a need for a reliable, conformable, flowable gap filling dielectric layer and method for reliably producing the same in a cost effective manner with adequate throughput.
An embodiment of the present invention provides a method of forming a dielectric layer on a substrate with improved gap filling results, by co-injecting an oxidant and water vapor into a deposition chamber, and injecting a silicon-containing gas or vapor into the deposition chamber, wherein the silicon-containing gas or vapor reacts with the oxidant in the deposition chamber according to a normal temperature process (e.g. from about room temperature to about 200xc2x0 C.) to deposit a layer onto the substrate.
An oxidant such as ozone may be used, wherein the ozone and the water vapor are heated in a showerhead to decompose the ozone prior to co-injecting the materials into the deposition chamber.
The showerhead is heated to a temperature up to about 200 C., typically about 90 C. to about 120 C.
The co-injecting is accomplished through first channels in a showerhead. The first channels are separate from second channels in the showerhead. The silicon-containing gas or vapor is injected through the second channels.
At least portions of the co-injecting and injecting steps may be performed simultaneously.
A capacitor stack configuration is disclosed which includes a substrate; a dielectric film having been deposited on an upper surface of the substrate; metallic interconnects having been deposited on the dielectric film and extending therefrom, and a gap fill layer. The metallic interconnects forming high aspect ratio gaps therebetween, wherein a depth of the high aspect ratio gaps is greater than a width of the high aspect ratio gaps. The dielectric fill layer is deposited over the metallic interconnects and gaps, to substantially fills the high aspect ratio gaps without leaving voids.
The dielectric fill layer is deposited by positioning the substrate, dielectric film and metallic interconnects into a deposition chamber; co-injecting an oxidant and water vapor into the deposition chamber; and injecting a silicon-containing gas or vapor into the deposition chamber; wherein the silicon-containing gas or vapor reacts with the oxidant in the deposition chamber according to a normal temperature process (e.g., including temperatures of about room temperature up to about 200xc2x0 C.) to deposit the dielectric fill layer.
The high aspect ratio gaps have an aspect ratio from about 7:1 to about 10:1, for example.
The dielectric fill layer comprises an oxide film containing a large number, e.g., up to about 50% of the available sites on the silicon atoms, of silanol groups within a silicon oxide network.
Other semiconductor structures than capacitors can also benefit from the gap filling layer of the present invention and method of producing the same.